1. Field of the Invention
The present invention relates to a method for manufacturing a field effect transistor (MOSFET: MOS Field Effect Transistor) having a very small gate length, which is achieved by using an SOI (silicon-on-insulator) substrate with a silicon layer formed on an insulating layer.
2. Description of the Related Art
An SOI substrate is constituted of an insulating layer and a silicon layer formed on the insulating layer. The structural features of the SOI MOSFET manufactured by using such an SOI substrate achieve advantages of a small parasitic capacitance, being latch-up free, a low soft error rate, relative ease in element isolation and the like. For this reason, an SOI MOSFET is considered to be ideal in application in a high-speed, low power consumption LSI.
In particular, since a depletion layer formed under a gate reaches a buried oxide film (BOX) under the SOI in a fully depleted (FD) device, the depletion layer capacitance can be reduced in the fully depleted device. Thus, an advantage is achieved in that the sub-threshold slope can be reduced to a value very close to the ideal value.
The SOI MOSFET manufacturing methods in the related art include the SOI nMOSFET manufacturing method disclosed in xe2x80x9cT, Ohno et al., IEEE Trans. On Electron Devices, 42, p.1481, 1995xe2x80x9d (hereafter referred to as the xe2x80x9cfirst related art methodxe2x80x9d). In the first related art method, a field oxide film for element isolation is first formed on an SIMOX (Separation by Implanted Oxygen) substrate achieved by forming a buried oxide film and a silicon layer on a silicon substrate at 100 nm and 56 nm respectively. Next, boron fluoride (BF2) ions are implanted into a body area enclosed by the field oxide film until a concentration of approximately 1017 cmxe2x88x923 is achieved. Then, ions of an impurity, i.e., BF2, are implanted for channel stopping at the edge of the body area. As a result, a higher density is achieved at the edge of the silicon layer.
In the next step, a gate oxide film is formed over a thickness of 7 nm on the body area. Then, N+ polysilicon is formed over a 30 nm thickness on the gate oxide film and the area ranging from one side of the field area through the center of the body area to the opposite side of the field area is patterned to form a gate electrode having a gate length of approximately 0.25 xcexcm.
In the following step, a silicon nitride (SiN) film and an N+ polysilicon film are formed at the side surface of the gate electrode constituted of the N+ polysilicon and a sidewall constituted of the SiN film and the N+ polysilicon film are formed through sidewall etching.
Then, phosphorus (P) is injected into the edge of the silicon layer through ion implantation to form a source drain area.
Next, after removing the N+ polysilicon film alone through wet-etching from the sidewall thereby achieving a sidewall exclusively constituted of the SiN film, a rapid thermal annealing treatment (RTA; rapid thermal anneal) is performed at 1000xc2x0 C. in order to activate the impurities.
A fully depleted SOI field effect transistor (MOSFET) achieving a very small gate length is manufactured through the first related art method as described above. In the first related art method, the threshold voltage (Vth) of the parasitic transistor formed at the edge of the body area is raised by implanting channel-stopping ions, and thus, a reduction in the off-leak current attributable to the occurrence of a hump is attempted.
Another SOI MOSFET manufacturing method in the related art is disclosed in xe2x80x9cNaka et al. Shingaku Giho, SDM 96-234, p.45, 1997xe2x80x9d (hereafter referred to as the xe2x80x9csecond related art methodxe2x80x9d).
The second related art method utilizes an SIMOX wafer achieved by forming a buried oxide film and a silicon layer over 100 nm and 55 nm respectively on a silicon substrate. A field oxide film for element isolation is formed first. Next, boron fluoride (BF2) and phosphorus (P) are injected into two body areas to constitute an nMOS and a pMOS through ion implantation to a concentration achieving a threshold voltage of 0.2xcx9c0.3 V.
Then, a gate oxide film is formed over a thickness of 7 nm on the two body areas. A non-doped polysilicon is formed over a thickness of 200 nm on the gate oxide film and then a gate electrode having a gate length of approximately 0.35 xcexcm are formed through patterning.
In the following step, a sidewall constituted of a silicon oxide (SiO2) film is formed at part of each body area, and then P and BF2 are injected into the nMOS area and the pMOS area through ion implantation. A single drain of the n MOSFET and pMOSFET are formed as a result. At the same time, an impurity is doped at each gate electrode. As a result, an N+ polysilicon gate electrode and a P+ polysilicon gate electrode are formed respectively at the nMOS area and the pMOS area.
In the next step, furnace annealing is performed at 800xc2x0 C. and then an RTA is performed at 1000xc2x0 C. to activate the impurities. Afterwards, a Ti silicide is formed on the sourcexe2x80xa2drain and also on the gate through a Ti silicide process.
A fully depleted SOI field effect transistor (CMOSFET) having a very small gate length is obtained through the second related art method as described above. The transistor obtained through this method, in which only a single sourcexe2x80xa2drain ion implantation each is implemented for the nMOS area and the pMOS area, has a xe2x80x9csingle drainxe2x80x9d structure.
While there is no detailed description in the publication, it is necessary to implement a photolithography process to implant ions at the edge of the nMOS body area for channel stopping in the first related art method. FIG. 17 illustrates the relationship between the gate electrode and the body area where the sourcexe2x80xa2drain are formed in a view taken from above the element. The two areas enclosed by the dotted lines in FIG. 17 indicate the edge of the body area where ions need to be implanted for channel stopping.
When implanting ions after a photolithography process, it is necessary to allow for an xe2x80x9calignment marginxe2x80x9d between the active area and the resist pattern where channel-stopping ion implantation is to be implemented. FIG. 18 shows the relationship between the active area and the resist pattern provided for channel-stopping ion implantation. As shown in FIG. 18, the width of the resist pattern constitutes the effective gate length. This means that the effective gate length is represented by the value obtained by subtracting the dimension required as the alignment margin from the dimension of the active area width. As miniaturization of elements is pursued with increasing vigor, the alignment margin is bound to become equal to or larger than the effective gate length. Accordingly, the first related art method poses a problem in that when attempting to reduce the element size, the width of the active area cannot be reduced.
FIG. 19 is a sectional view of an element formed at an SOI substrate having a silicon layer formed over an insulating layer. It shows an area (A) where channel stopping is required, an area (B) where channel stopping is not required and an area (C) where channel stopping ions have not been implanted. The area (A) where a high impurity concentrations must be achieved through channel stopping ion implantation is the hatched area in the sectional view presented in FIG. 19 where the film thickness of the silicon layer is reduced ranging over approximately 50 nm from the edge of the body area. In this area, the gate oxide film constituted of the field oxide film has a large thickness. However, since the film thickness of the silicon layer is small, the quantity of the impurity contained in the silicon layer is smaller than the quantity in the area with a larger film thickness. This results in a lowered threshold voltage of the parasitic transistor which manifests hump characteristics shown in FIG. 20. In FIG. 20, the vertical axis represents the drain current (Ids), the horizontal axis represents the gate voltage (Vg), the solid line represents the main transistor characteristics and the dotted line represents the parasitic transistor characteristics. The manifestation of hump characteristics such as those shown in FIG. 20 leads to an increase in the off-leak current (Ioff).
The area (B) in FIG. 19 is an area where it is not necessary to achieve a high impurity concentration. However, when a resist mask is provided through photolithography over an area other than the area where the impurity is injected, the channel stopping impurity is also injected into this area to raise the threshold voltage and, as a result, the area can no longer be included in the effective gate length.
In the second related art method, ions are implanted to form the sourcexe2x80xa2drain from the outside of the sidewall. This allows inconsistency in the film thickness of the sidewall to increase the range over which the gate electrode and the sourcexe2x80xa2drain overlap, which, in turn, leads to an increase in the difference between the physical gate length and the electrical gate length. Or, the film thickness inconsistency may eliminate any overlap of the gate electrode and the sourcexe2x80xa2drain instead and, in such a case, an offset structure is assumed. In either case, there is a problem in that the current value at the transistor fluctuates greatly.
The film thickness of the sidewall is determined by the length over which the impurity is diffused at the sourcexe2x80xa2drain. The impurity diffusion length, in turn, is greatly affected by the temperature at which the heat treatment is performed and also by the impurity concentration. In the second related art method, in which the impurity is injected into the gate electrode concurrently while injecting the impurity into the sourcexe2x80xa2drain, relatively rigorous restrictions must be imposed with regard to the ion implantation conditions and the heat treatment conditions in order to prevent depletion from occurring at the gate electrode.
Namely, (1) the heat treatment must be performed at a high temperature of approximately 1000xc2x0 C. to fully diffuse and activate the impurity in the gate electrode, and (2) a high concentration equivalent to a dose of 5xc3x971015 cmxe2x88x922 must be assured since it is necessary to achieve an impurity concentration of 1020 cmxe2x88x923 or higher in the 20 nm polysilicon.
For the reasons (1) and (2) stated above, it is necessary to allow for a large film thickness of up to 100 nm at the sidewall. However, the absolute value of the film thickness inconsistency becomes larger as the film thickness at the sidewall increases, resulting in a problem of pronounced inconsistency in the transistor characteristics.
In addition, since an nMOS transistor has a different sourcexe2x80xa2drain impurity diffusion constant from that of a pMOS transistor, it is difficult to achieve optimization for both transistors. This is a problem unique to CMOSFETs.
Furthermore, the in-plane inconsistency of the sidewall film thickness is attributed to the film thickness inconsistency resulting from the sidewall etching as well as the inconsistency in the thickness of the oxide film that is formed. Thus, it is difficult to achieve effective control on the sidewall film thickness.
The present invention has been completed to address the problems of the related art discussed above. A first object of the present invention is to provide a method for manufacturing a field effect transistor achieving a small gate length, which is free from the adverse effect of a parasitic transistor, minimizes the occurrence of a hump and allows an nMOS and a pMOS to be formed next to each other over a small distance.
A second object of the present invention is to provide a method for manufacturing a field effect transistor in which the fluctuation of the current value is minimized by suppressing the short channel effect and eliminating any inconsistency in the film thickness at the sidewall.
In order to achieve the first object, a first field effect transistor manufacturing method according to the present invention, through which a gate electrode, a sourcexe2x80xa2drain are formed on an SOI substrate having a silicon layer formed on an insulating layer, comprises:
a step in which a field oxide film for element isolation is formed;
a step in which an active nitride film is wet-etched until its film thickness is reduced to allow an edge of the silicon layer to be exposed; and
a step in which ions of a channel stopping impurity are implanted vertically or at an angle only into the edge of the silicon layer through self-alignment by using the active nitride film as a mask.
In addition, in order to achieve the second object, a second field effect transistor manufacturing method according to the present invention, through which a gate electrode, a sourcexe2x80xa2drain are formed on an SOI substrate having a silicon layer formed on an insulating layer, comprises:
a step in which the gate electrode is etched;
a step in which ions are implanted into the sourcexe2x80xa2drain at an energy level at which all the impurity is injected into the silicon layer constituting the sourcexe2x80xa2drain;
a step in which a heat treatment is implemented at a low temperature under 1000xc2x0 C. in order to activate the impurity at the sourcexe2x80xa2drain.